1. Field of the Invention
This invention relates generally to the field of digital interface design and, more particularly, to a system for transferring data from one clock domain to another clock domain.
2. Description of the Related Art
The design of interfaces plays a significant role in the implementation of many digital systems. One example of such digital system is a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) system. FIG. 1 illustrates a common implementation of a DDR SDRAM system that includes a DDR SDRAM Controller coupled to a DDR SDRAM unit through an interface unit (memory I/O), with the memory I/O coupled to the DDR SDRAM unit through a set of pad circuits. In a DDR SDRAM, read-data is accompanied by a corresponding trigger signal, commonly referred to as a DQS (DQS) signal. DQS is often used by the memory I/O, which may be coupling the DDR SDRAM to an Application Specific Integrated Circuit (ASIC), to sample and latch the read-data.
Generally, once the read-data has been latched inside the Memory I/O, it needs to be transferred to the clock domain of the ASIC. The transferring of the read-data often includes registering or latching the read-data a second time. A second registering or latching of the read-data is many times accomplished using a first-in-first-out (FIFO) buffer. Most systems require a free-running trigger signal or clock signal to latch the data into the FIFO buffer. Therefore, in the case of a DDR SDRAM system, a DQS provided by the DDR SDRAM would have to be free-running. A DQS provided by a DDR SDRAM system, however, is usually not free-running.
A common approach to solving this issue may be to generate a clock running at a frequency commensurate with a frequency of a DQS, and delaying the clock to bring it in phase with DQS. Such design would usually require a phase locked loop (PLL) or a delay locked loop (DLL). A PLL and/or DLL design may be time consuming and in many cases too expansive. Therefore, there exists a need for a simpler system and method for transferring data, such as read-data for a DDR SDRAM, from one clock domain, such as a clock domain of the DDR SDRAM, to another clock domain, such as a clock domain of an ASIC, when a trigger signal, such as a DQS, or clock signal provided with the data for the purpose of registering or latching the data, is not a free-running trigger signal or clock signal, respectively.